Table-top EUV ptychography self-calibrates chip inspections

Researchers in China have built a table-top 17.9-nm extreme-ultraviolet ptychography system that self-calibrates full 3D pose errors for semiconductor metrology. The approach resolved 43.5-nm chip features, corrected distortions, and detected defects, pointing to faster nondestructive inspection for advanced devices.

Why it matters: - Semiconductor features keep shrinking, but EUV inspection remains hard because the wavelength is short and the imaging geometry is highly sensitive to alignment errors. - A reliable table-top system could make nondestructive nanoscale metrology more practical for advanced chip manufacturing. - The method targets reflective and tilted-geometry imaging, which is relevant beyond EUV and could extend to visible light, X-rays, and electron beams.

What happened: - Researchers led by Professor Yishi Shi at the University of Chinese Academy of Sciences developed a table-top 17.9-nm EUV grazing-reflection ptychography system with full-pose self-calibration. - The paper was published in Light: Advanced Manufacturing. - The system combines full-system forward modeling, feature-domain loss evaluation, and automatic-differentiation-based optimization. - The original source DOI is 10.37188/lam.2026.112.

The details: - The imaging model jointly handles the diffraction distance, 3D illumination angle, 3D detector pose, and scanning positions. - The reconstruction loop recovers the sample, the illumination probe, and the system pose parameters at the same time. - The detector sits normal to the outgoing beam while the sample remains strongly tilted in a grazing-reflection setup of about 70 degrees. - That geometry produces nonuniform sampling on the Ewald sphere and creates distortions that depend on system alignment. - Conventional calibration methods usually correct only one or two pose parameters, leaving residual artifacts. - On a customized wafer sample, full-pose self-calibration delivered the best image quality among the tested reconstruction methods. - The reconstruction clearly resolved fine structures near the center of a Siemens star and point-like defects. - The method significantly suppressed geometric distortions in wafer patterns, improving critical-dimension measurements. - On a real chip sample, the system resolved grating structures with a 43.5-nm half-pitch. - The chip reconstruction matched scanning electron microscopy measurements. - The system also identified contamination and scratch defects on the chip. - The study examined feature-domain loss functions, sensitivity to system-parameter errors, coupling among pose parameters, and low-dose performance. - The work was supported by the National Key Research and Development Program of China, the National Natural Science Foundation of China, and the Fundamental Research Funds for Central Universities.

Between the lines: - The main advance is not only higher resolution, but a way to remove the calibration bottleneck that has limited reflection-mode EUV ptychography. - By folding hardware geometry into the reconstruction model, the approach reduces reliance on precise manual alignment. - That makes the method more attractive for industrial metrology, where speed, repeatability, and robustness matter as much as raw resolution.

What's next: - The researchers say the framework could guide future reflective ptychography system design and algorithm development. - The approach may help push EUV ptychography from lab demonstrations toward manufacturing inspection. - Likely applications include nondestructive characterization of advanced semiconductor devices and emerging 3D heterogeneous integrated structures. - The broader method could be adapted to other imaging systems that use reflective or tilted geometries.

The bottom line: - A compact EUV ptychography setup has shown that full-pose self-calibration can deliver nanoscale chip inspection without demanding ultra-precise hardware alignment.